The present invention relates to a clock and data regenerator for different data rates having a phase and frequency control device.
Phase locked loops are used in order to recover the clock signal from a received binary signal, and to obtain a regenerated data signal using this clock signal.
In a clock regeneration device, the control loop is chosen to have a narrow bandwidth so that the frequency and phase remain constant even in the event of a long sequence of zeros or ones. However, a stable phase locked loop has a very narrow catchment range. Thus, the clock recovery operates only in a very narrow frequency range (i.e., essentially only one quite specific bit rate).
A phase locked loop (PLL) which has a phase discriminator and a frequency discriminator is described in xe2x80x9cFrequency Detectors for PLL Acquisition in Timing and Carrier Recoveryxe2x80x9d by David G. Messerschmitt, IEEE Transaction Communication, Vol. COM-27, pp. 1288-1295, September 1979. The frequency discriminator is first used to set the oscillator frequency approximately, and the phase angled between the clock signal that is produced and the data signal is then kept constant via the phase locked loop. In practice, these phase locked loops have a catchment range of approximatelyxc2x130% of the data signal frequency (bit rate).
If the clock regeneration is intended to be used for different data rates, then the catchment range of the PLL is frequently inadequate.
An apparatus for obtaining a clock signal from a data signal using a bit rate identification device for the received data signal is described in Laid-Open Specification DE 197 04 299 A1. The bit rate identification device is supplied with various reference signals, which allow the flank densities of the received data signal and of the reference signals to be compared. The result of this comparison is used to set a frequency divider in the feedback path such that the phase control becomes successfully effective. This apparatus is particularly suitable for a small number of bit rates, which are known at the receiving end.
An object of the present invention is, therefore, to provide a clock and data regenerator which reliably processes different bit rates of the data signal without any gaps. The clock and data regenerator is intended to be developed such that differently coded data signals can also be processed.
One advantage of the present invention is the universal applicability of the regenerator by virtue of its wide operating range. Generally, there is no need for a reference clock, but such a clock can be used in order to allow the frequency divider to be pre-set.
Another advantage is achieved by a further frequency discriminator, which sets a frequency divider arranged in the feedback loop of the control loop and adjusts a comparison frequency, which is obtained from the oscillator frequency, to such an extent that it enters the catchment range of the first frequency discriminator.
In an embodiment, the frequency divider is adjusted in steps while, in alternative embodiments which operate at higher speeds, the divider can be pre-set directly on the basis of the measurement results from the further frequency discriminator. The two frequency discriminators can, of course, be combined in the circuitry.